Implementation of grid-connected miniature solar inverter using C2000 MCU

Summary

The rapid development of renewable energy applications will trigger the fourth industrial revolution. Photovoltaic power generation is a key part of the overall renewable energy programme. Among all solar inverters, miniature solar inverters are a vital component.

This article will show you how to design a low-cost, high-performance miniature solar inverter using a TMS320F2802. In addition, the article will discuss how to implement a 220W output miniature solar inverter using a crossover active clamp flyback and SCR full bridge, and introduce the complete system firmware architecture and control method. Finally, the article will show you the lab waveforms.

1 Overview

1.1 Introduction to Solar Inverter

Materials, energy and information are the three major elements of human survival and development. Every new discovery of energy use will greatly change and promote the development of modern civilization:

Â· The invention of the steam engine allowed us to enter the machine era.

Â· The invention of electricity allowed us to enter the electrical age.

Â· The invention of semiconductor transistors allows us to enter the information age.

The current development and utilization of renewable energy will trigger the fourth industrial revolution; among all renewable energy utilization methods, photovoltaic power generation is a key component of the development of the entire renewable energy. According to the World Energy Organization, as traditional energy sources (such as coal, oil, etc.) are gradually depleted, renewable energy will become the main source of energy for human beings. Figure 1 shows the development trend of the world's energy.

Figure 1 World Energy Development Trend

Governments have paid great attention to the development of renewable energy. In 2007, the Chinese government stated that â€œrenewable energy can meet the needs of the country's long-term development plan.â€ In 2008, the Chinese government issued the 11th five-year development plan for renewable energy. According to the plan, China's installed capacity of photovoltaic power generation in 2010 needs to reach 250 billion watts; it is estimated that by 2020, China's photovoltaic power generation capacity will reach 50 billion watts, of which grid-connected photovoltaic power generation accounts for 75%.

The main advantages of solar photovoltaic power generation include:

Â· Solar energy is very rich and endless.

Â· The material for producing PV panels is widely distributed and abundant in reserves.

Â· The system structure is simple and the conversion efficiency is high.

Â· No pollution, and can be recycled.

Â· Photovoltaic battery has long life and low maintenance cost.

Disadvantages of solar photovoltaic power generation include:

Â· Low power density and large footprint.

Â· Power generation is limited by natural conditions and cannot be generated without the sun.

Â· The unit production cost is high.

1.2 Classification of photovoltaic power generation systems

According to the application environment, the photovoltaic power generation system can be divided into a non-incorporated solar inverter system and a networked solar inverter system.

The non-incoming solar inverter system is mainly used for independent photovoltaic power generation systems, which is suitable for communication, testing and application in home, rural, island, remote areas, urban lighting and power systems. 2 is a system structural diagram depicting main components of a solar panel assembly, a solar inverter unit, an energy storage unit, and an electrical load.

Figure 2 Non-networked solar inverter system

The incoming solar inverter system is mainly used to connect with the traditional power grid. The solar inverter connects the electric energy from the PV panel to the traditional power grid. The main components are solar panels, solar inverters, smart two-way fuel gauges, household electrical loads and Traditional power grid, etc. (see Figure 3)

Figure 3 Into the network solar inverter system

1.3 PV board electrical characteristics

Solar inverter power output changes are almost directly related to sunlight, but the current is reduced much faster than the light level drops. At very low light levels, PV panels typically generate 16V, but current is minimal.

In addition, as the PV panel temperature increases, the voltage output drops, and vice versa. The output curve varies with lighting conditions, temperature, etc., as shown in Figure 4.

The solar inverter must operate under the MPP to get the maximum power from the PV panel. This is achieved by the maximum power point control loop (Maximum Power Point Tracker, MPPT).

Figure 4 PV board electrical characteristics

1.4 Solar inverter topology change

As the illuminance changes, the PV panel's output voltage ranges from 20 to 45 volts, so if the grid application requires a higher output voltage, then the PV panel is usually considered and connected in series to obtain a high input voltage and an inverter is used. Realize power conversion. This topology is called a â€œcentral inverterâ€, as shown in Figure 5(a); its main features are:

Â· 10 to 250kw, 3 phases, several parallel strings

Â· High converter efficiency, low cost and low reliability

Â· Non-optimal MPPT

Â· Usually used in power plants

Figure 5 Central and string topology

Another application is to connect PV panels in series at all string branches to achieve energy conversion. Use an MPPT module to get the maximum power of the PV panel. This topology is called a â€œstring inverterâ€, as shown in Figure 5(b); its main features are:

Â· 1 to 10kw, typical residential application.

â€¢ Each string branch has its own inverter for better MPPT.

â€¢ Each string can have a different orientation.

Â· Three-phase inverter for output power of more than 5km.

Although such a string inverter can achieve more power collection efficiency, when a series PV panel is shaded, the power collection of the string branches also decreases, as shown in Fig. 6(a). This problem can be solved if an MPPT module is placed to collect power from all PV panels. This topology is called a "micro inverter", as shown in Figure 7.

Figure 6 Effect of shadow on power collection

Figure 7 Micro Inverter Topology

Clearly, in the case of micro-inverters, the â€œdistributed MPPTâ€ architecture increases the cost per PV panel; however, efficiency can be increased by 5% to 25% by recovering the following efficiency losses:

Â· PV board mismatch loss (3% to 5%)

Â· Partial shadow loss (5% to 25%)

Simple system design, more relaxed fault tolerance (0% to 15%)

Â· Suboptimal MPPT loss (3% to 10%)

Â· In addition, increase safety and building area (roof) utilization

Therefore, if we choose a micro-inverter topology, we will sacrifice converter efficiency, but it will make power collection more efficient.

2 hardware design

2.1 System structure diagram

In our solar inverter solution, we chose a cross-reverse plus SCR full-bridge topology for industrial frequency inversion. All control is only one MCU (2802x), and there is also an RS485 or PLC interface for communication. Figure 8 shows a block diagram of such a miniature solar inverter. For specific specifications, please refer to Attachment A.

This topology has the following characteristics:

Â· Simple system structure

Â· High efficiency, low cost

Â· Complete isolation, high reliability

Â· Reactive power compensation cannot be achieved

Figure 8 Micro solar inverter system structure

2.2 Auxiliary power supply design

In the miniature solar inverter, we need an auxiliary power supply that can output multiple voltages to the A/D sampling circuit, the driving circuit, the MCU controller, and the like. On the other hand, this auxiliary power supply must be completely isolated from the primary side to the secondary side.

Therefore, we choose the LM34927 chip; this chip has the following characteristics:

Â· Wide input range from 9 to 100V

Â· Low cost, integrated 100V, low-side switch

Â· Constant on-time (COT) control scheme no loop compensation, and has superior transient response.

Â· Full protection features, including an adjustable UVLO.

Figure 9 shows a typical application schematic of the LM34927. From this schematic, we know that the primary side of the LM34927 is a buck circuit and the secondary side is a flyback topology for isolation.

Figure 9 LM34927 typical application schematic

2.3 Active Clamp Flyback Designed as Isolated Front End Converter

2.3.1 Overview of Active Clamp Flyback Converters

Figure 10 shows the combination of active clamp circuits in the basic flyback topology. In the figure, the flyback transformer is replaced by an equivalent circuit model, which exhibits magnetization and leakage inductance (Lr represents the total transformer leakage inductance reflected by the primary side except the external inductance).

Switches Q1 and Q2 appear with their associated body diodes. Cr represents the parallel capacitance of the parasitic capacitance of the two switches. This device capacitor, which resonates with Lr, implements the zero voltage switch (ZVS) of Q1.

With the active clamp circuit, the transistor turn-off voltage spike is controlled, the transformer leakage is recovered, and the ZVS of both the main switch (Q1) and the auxiliary switch (Q2) is possible.

The cost of these advantages is the need for more power stage components and higher control circuit complexity (two switches versus one switch).

To describe the operation of this circuit, we assume that:

Â· Ideal switch assembly

â€¢ The magnetizing current is always non-zero and positive.

Â· Lr (including transformer leakage inductance) is less than transformer magnetizing inductance Lm (usually 5% to 10% of Lm)

â€¢ Lr stores enough power to completely discharge the Cr and turn on the body diode of Q1.

Figure 10 Simplified schematic of an active clamp flyback converter

2.3.2 Active Clamp Flyback Design Zero Voltage Switch Considerations

In order to achieve ZVS of Q1, Q2 must be turned on in the resonant inductor current drop interval. Otherwise, the resonant inductor current reverses (again, becomes positive again), which recharges Cr and loses ZVS (or at least partially loses). Therefore, the delay between Q2 shutdown and Q1 turn-on is critical to ZVS operation. The optimal delay value is one quarter of the resonance time of Lr and Cr:

Therefore, it is best to let the dead time be between Q1 off and Q2 on, less than Tdelay, to achieve partial ZVS state.

Even if the stored energy in Lr is not enough to completely discharge the switched capacitor Cr, thus minimizing the potential voltage stress of Q1 and Q2 (and achieving higher converter efficiency), we must carefully design the resonant inductor Lr, resonant capacitor Cr and clamp The parameter of the bit capacitance Cc.

2.3.2.1 Resonant Inductance Lr Design

After determining the Lm value, the resonant inductor can be designed. As mentioned earlier, we assume that its value is a small fraction of Lm (usually 5% to 10% of Lm).

To achieve ZVS operating point and Cr value, to achieve ZVS, Lr must be large enough to completely discharge the switched capacitor.

The Lr design is difficult because the resonant capacitor voltage (Vcr) is a function of the Lr value, as in the equation below:

However, in practical designs, the resonant inductor voltage is relatively small (relative to Vin+NVo) and can solve the minimum Lr approximation required to achieve the ZVS state:

In applications where high output voltages are required, the special output rectifier soft switching characteristics are more desirable than implementing the main switch ZVS.

2.3.2.2 Clamp Capacitor Cc Design

According to the Lr design, select the value of the clamp capacitor. The resonant frequency formed by the clamp capacitor and the resonant inductor is sufficiently low that the power switch will not exhibit excessive resonant ringing when the switch is turned off. However, the use of excessive clamp capacitance values â€‹â€‹does not result in improved clamping performance and at the expense of larger (and more expensive) capacitors. A better compromise is to choose a capacitor value that causes the clamp capacitor and resonant inductor to form half the resonance time, exceeding the maximum turn-off time of Q1. therefore:

Among them, DHL indicates the maximum input voltage operation, and fs is the working switching frequency of Q1 and Q2.

The capacitor's rated voltage must exceed NVo and the excess voltage is the pressure drop of Lr:

The resonance time of the clamp capacitor and the resonant inductor can be calculated by the following equation:

2.3.3 Open-loop simulation of active clamp flyback

Figure 11 shows an open-loop simulation model of this active clamp flyback. The following values â€‹â€‹are used for this simulation: input voltage Vin=36V, main MOSFET switching frequency fs=65kHz, resonant inductor Lr=0.5Î¼H, resonant capacitor Cr=1nF, clamp capacitor Cc=10Î¼F, maximum duty cycle D of main switching MOSFET = 0.6, while the load Rload = 100 Î©.

Figure 11 Open-loop simulation model of active clamp flyback

(The red waveform is VGS and the green waveform is VDS)

Figure 12 VDS and VGS simulation waveforms of Q1

Figure 12 shows the gate-driven voltage rise after the drain-to-source voltage drops to zero, so Q1 achieves ZVS verification. In addition, the voltage spike of the VDS is clamped to Vin+NVout, which means that the active side is implemented on the primary side.

Figure 13 Simulation output voltage waveform

2.4 Isolated MOSFET Bridge Drive Circuit Design

In order to achieve complete isolation from the primary side to the secondary side, in addition to auxiliary power isolation, A/D sampling and drive circuit isolation are required.

Since the MCU is placed in the secondary side and the main switching MOSFET is on the primary side, we must transfer the secondary side control signal to the primary side to control the MOSFET.

In order to transfer the control signal from the secondary side to the primary side, a high speed digital isolator can be selected to boost the low side driver chip. Figure 14 shows the schematic of this isolated MOSFET high and low side driver.

Figure 14 Schematic diagram of isolated high and low side drivers

In this application, isolated MOSFETs have many features, including:

Â· Simple structure, easy to implement

Â· +600V full working range

Â· 4kV ESD protection

Â· Bootstrap work

Also, be aware of the initial state of the high speed digital isolator; otherwise, it will damage the main switching MOSFET.

Table 1 High-speed digital isolator function table

(PU=Power-on; PD=Power-down; X=Ignore; H=High level; L=Low level)

3, firmware design

3.1 Firmware Specification

3.1.1 Functional Specifications

The system firmware includes the following features:

1, on / off. The user can turn the system on or off by pressing the on/off button. Software settings must enable this feature.

2, automatic on / off. If you need to turn on the status, the system will automatically turn on. When the state is not suitable for power transmission to the grid, the system maintains standby mode and monitors state changes. If the system is already on, the system automatically shuts down when the status is not suitable for power.

3. The software starts up. When the system must be turned on, it starts from a zero current supply state, and the PWM turns on at the zero crossing point, thereby reducing the inrush current to the grid.

4, LED control. The system has a status LED indication. When the system is in standby mode, the corresponding LED flashes once every 1.2 seconds. When the system is turned on, the LED flashes once every 2.4 seconds. When a fault occurs, the LED continues to illuminate.

5. User control keys. The inverter has a user button. This user button turns the inverter on or off and also clears the fault. When the system is in standby mode, if the button is pressed for more than 1 second, it will be turned on if the condition is met. If the system is already on, the system turns off when the button is pressed for more than 1 second. When a fault occurs and the system is in the fault mode, pressing the user button for more than 1 second clears the fault and enters standby mode again.

3.1.2 Measurement

In order to control and monitor the system status, the following measurements need to be calculated:

Â· Grid voltage RMS

Â· Grid frequency

Â· Inverter output effective power

Â· Input power

Â· Input PV voltage

Â· temperature

3.1.3 Protection

The system has some basic protection features.

1. Primary side surge current protection. When a short circuit or main inductor causes an inrush current, PWM prefers to enter CBC mode; however, when CBC is more than three times, the system shuts down and enters fault mode.

2. Secondary side overvoltage protection. When the SCR is not normally turned on, a secondary side ultrahigh voltage occurs. The system shuts down and enters failure mode.

3. Output over current protection. When the output current exceeds the threshold, an output overcurrent occurs. The system shuts down and enters failure mode.

4, grid voltage / frequency is too high / too low protection. If the system is already on, the system shuts down during five grid periods when the grid voltage/frequency is outside the normal range.

5. Anti-island suppression protection. If the island condition is reached, the system shuts down within 4 seconds. If it returns to the normal state, the system restarts within 1 second.

6, over temperature protection

3.1.4 Network Converter Controller

In order to transmit power to the grid, the following controller algorithms must be implemented in the system:

1. Phase-locked loop (PLL) controller. The PLL controller is used to synchronize with the grid voltage, which provides a reference phase to the current controller.

2. Network current controller. The current controller ensures that the output current is sinusoidal and follows the current reference to balance the input power and output power.

3. Maximum power point tracking (MPPT). MPPT is used to get the solar panel into maximum power output.

3.2 Firmware structure

3.2.1 Background and tasks

The entire firmware system is a forward background system. Figure 15 shows the background structure.

Figure 15 background structure

In this system, there is a 1ms task and four 4ms tasks.

1, 1ms task A0. 1ms regular tasks. In this task, LED control is performed. In addition to this, the PLL controller is also located in this task.

2, 4ms task A1. A1 4ms regular task. State machine processor.

3, 4ms task A2. A2 4ms regular task. All measurements are calculated in this task.

4, 4ms task A3. A3 4ms regular task. The user key detection is here, and the detection exceeds or does not reach the operating state range, and a fault command is issued.

5, 4ms task A4. A4 4ms regular mission. MPPT controller and debugging support.

3.2.2 System State Machine

Figure 16 state machine

Figure 16 shows the state machine processed in task A1. Different states represent different modes of operation.

There are four status modes in this system:

Â· Power on

Â· Standby

Â· Open

Â· Fault

Power-on mode is a transition mode for system power-on. In this mode, the system performs some initialization, after which the system automatically enters standby mode.

Standby mode is a mode in which the system waits for an open command. All PWM and SCR control signals are turned off. In this mode, all measurements are valid. The system detects the external status and checks if the system can be turned on.

When the system successfully boots from standby mode, the system enters the on mode. In this mode, all PWM and SCR control signals are turned on. The system begins to transmit power to the grid.

In the event of a fault, the system enters fault mode and all PWM and SCR control signals are turned off. If the fault is cleared, the system automatically returns to standby mode.

3.2.3 Interrupt Service Procedure

The system's Interrupt Service Routine (ISR) has the following functions:

â€¢ Read ADC results and partial measurement calculations.

Â· Incoming current controller

Â· SCR on/off control

Â· Emergency protection. Primary side surge current, secondary side overvoltage and output current protection.

Â· Debug support. Record debug data to the buffer.

Figure 17 ISR flow chart

3.3 Network Converter Controller

Figure 18 shows the entire network converter structure.

Figure 18 controller structure

3.3.1 PLL Controller

Figure 19 shows the PLL controller system

Figure 19 PLL control system diagram

The PLL system consists of the following parts:

Â· Phase error detection. The phase error between the reference and the sine wave output is detected. This detection function is implemented in 1ms task A0.

Â· PLL controller. Closed loop controller, the controller executes in 1ms task A0.

Â· Sine wave generator. A sine wave is generated based on frequency and sampling time; this is done in the ISR.

3.3.2 Current Controller

In order to design a current loop, the object model must first be built. A small signal model can be used here.

Figure 20 flyback circuit

Assume that the flyback circuit is as shown in Figure 6; in addition, it is assumed to operate in continuous mode.

Figure 21 Flyback continuous mode current

If the MOS of the primary side is turned on, the primary side current increases, Lp charges, and energy is stored therein. Therefore, the following equation can be obtained:

If Q1 is turned off, the energy is immediately transmitted to the secondary side, and ip quickly drops to zero. On the secondary side, the diode is turned on, the secondary inductor is connected to the load, and C is charged. Equation (2) can be obtained.

The main inductance Lp and the secondary inductance Ls have the following relationship:

Combine equation (3) with equation (2) to get:

Using this average state space method, if the duty factor is d, the following equation can be obtained:

The other program (5) is slightly modified to get:

Remove high-order infinitesimal elements to get:

therefore, with The relationship is:

The steady state of D is:

The controller loop is:

Figure 22 Current Controller Loop

When using a PI controller, the controller calculates a frequency of 22 kHz. The open loop bandwidth must be set to 1 to 2 kHz.

Figure 8 shows that the closed loop feedback must be the primary side current ip, but in a real system, it is the intermediate point current when Q1 is on. If the converter is operating in continuous mode, the relationship between the primary and secondary currents is:

In order to obtain a sine wave output current, the secondary average current must be a sine wave; therefore, the feedback circuit must be changed to the following model: